1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to an improved process of incorporating barrier atoms within active areas of a semiconductor substrate laterally adjacent to a trench isolation structure to enhance properties of the isolation structure and of transistors within the active areas.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are interconnected by conductors which extend over a dielectric that separates or xe2x80x9cisolatesxe2x80x9d those devices. Implementing an electrical path across a monolithic integrated circuit thus involves selectively connecting devices which are isolated from each other. When fabricating integrated circuits it is therefore necessary to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for a MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS processing involves oxidizing field regions of a silicon-based substrate between device areas. The oxide grown in the field or isolation regions is termed xe2x80x9cfield oxidexe2x80x9d. The field oxide is grown during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. By growing a thick field oxide in field regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems associated with LOCOS. First, a growing field oxide extends laterally as a bird""s-beak structure. In many instances, the bird""s-beak structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery, causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topographical disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field regions(i.e., field areas of small lateral dimension) relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs. Field-oxide-thinning produces problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the xe2x80x9cshallow trench processxe2x80x9d. The shallow trench process is particularly suited for isolating densely spaced active devices having field regions less than one micron in lateral dimension. Conventional trench processes involve the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then refilling the shallow trench with a deposited dielectric. The trench is then planarized to complete formation of the isolation structure. The trench process eliminates bird""s-beak and channel-stop dopant redistribution problems. In addition, the isolation structure is fully recessed, offering at least a potential for a planar surface. Still further, field-oxide thinning is reduced in narrow isolation spaces, and the threshold voltage is constant as a function of channel width.
While the conventional trench isolation process has many advantages over LOCOS, the trench process also has problems. Because trench formation involves etching of the silicon substrate, it is believed that dangling bonds and an irregular grain structure form in the silicon substrate near the walls of the trench. Such dangling bonds may promote trapping of charge carriers within the active areas of an operating transistor. As a result, charge carrier mobility may be hindered, and the output current, ID, of the transistor may decrease to an amount at which optimum device performance is unattainable.
Further, during subsequent anneal steps (e.g., thermal oxidation for gate oxide formation), the irregular grain structure may provide migration avenues through which oxygen atoms can pass from the field oxide to the active areas. Moreover, the dangling bonds may provide opportune bond sites for diffusing oxygen atoms, thereby promoting accumulation of oxygen atoms in the active areas near the edges of field oxide. Oxygen atoms present in active areas of the silicon may function as electron donors. Thus, inversion of silicon may occur in subsequently formed p-type active areas near the walls of the isolation trench. Further, the edge of a device may not conduct as much current as the interior portion of the device. Therefore, more charge to the gate of a transistor may be required to invert the channel than if no inversion occurred, causing threshold voltage, VT, to shift undesirably from its design specification.
In a subsequent processing step the semiconductor topography may be subjected to a high temperature anneal to activate impurity species in the active areas and to annihilate crystalline defect damage of the substrate. Unfortunately, impurity species, such as boron, in the active areas may undergo diffusion into the isolation region when subjected to high temperatures. As a result, the threshold voltage in the isolation region may decrease. Thus, migration of impurities into the isolation region may lead to current inadvertently flowing between active areas, defeating the purpose of having the trench isolation region in the first place.
It is therefore desirable to develop a technique for forming a trench isolation structure between active areas in which problems related to dangling bonds and irregular grain structure in the active areas are alleviated. Such a technique is necessary to inhibit charge carriers and oxygen donors from being entrapped in the active areas. Yet further, it is desirable that impurity species be prevented from migrating into the trench isolation structure so that current leakage between active areas may be inhibited.
The problems noted above are in large part solved by the method hereof for isolating active areas within a semiconductor substrate. That is, the present invention contemplates the formation of a trench isolation structure between active areas of a semiconductor substrate. Advantageously, barrier atoms are incorporated in the active areas adjacent to the walls of the trench to enhance the properties of both the isolation structure and of device performance within the active areas adjacent the isolation structures.
According to an embodiment of the present invention, a semiconductor topography is provided in which a masking layer is formed above a semiconductor substrate. An opening is formed vertically through the masking layer, and a dielectric spacer material is deposited across the exposed surface of the topography. The spacer material is then anisotropically etched to form spacers directly adjacent to opposed sidewall surfaces of the masking layer opening. The spacers are strategically placed above regions of the substrate into which barrier atoms are to be subsequently incorporated. An isolation trench is then etched into the semiconductor substrate between the spacers. The resulting trench is relatively shallow and is interposed between ensuing active areas of the semiconductor substrate.
An oxide (i.e., SiO2) layer may be thermally grown within the trench on the exposed edges of the substrate. Oxide may then be deposited using chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) into the trench and across the masking layer surface. Chemical-mechanical polishing may be used to planarize the upper surface of the masking layer. The oxide may then be etched down to an elevation commensurate with the upper surface of the semiconductor substrate. The spacers may be concurrently etched down to near the surface of the substrate. The resulting trench isolation region includes both a thermally grown oxide and a deposited oxide. As described previously, a shallow isolation trench which is filled with a deposited oxide has many benefits over LOCOS isolation structures. However, deposited oxide is generally less dense than thermally grown oxide and has an altered stoichiometry that can cause changes in the mechanical and electrical properties of the film. Thermally grown oxide, on the other hand, has a generally uniform stoichiometry arranged for consistent electrical isolation. Accordingly, thermally grown oxide is strategically arranged at the periphery of the trench adjacent to the active areas which require electrical isolation. The remaining bulk of the isolation structure is CVD oxide.
The semiconductor topography is then exposed to thermal radiation in a barrier-entrained ambient. As a result, barrier atoms, e.g., nitrogen atoms, migrate into exposed areas of the semiconductor topography, particularly into areas of the semiconductor substrate directly under the spacers and adjacent to the walls of the trench. The masking layer inhibits the barrier atoms from diffusing into other regions of the substrate. The spacers are thin enough to allow barrier atoms to pass through them to the substrate therebelow. The masking layer and any remaining portions of the spacers are removed in preparation for the growth of a gate oxide across the substrate.
Barrier atoms thusly placed in the semiconductor substrate contribute many useful features to active area isolation. They may fill voids in an irregular grain structure which may have resulted when etching the trench. The barrier atoms may also bond with available silicon atoms such that opportune bond sites no longer exist. Further, the barrier atoms may fill interstitial sites between silicon atoms. Thus, barrier atoms may block grain-boundary diffusion pathways into and out or the active areas. Therefore, impurities are inhibited from passing into the field oxide and oxygen atoms are inhibited from passing into the active areas. Problems associated with these occurrences, such as current leakage between active areas and edge inversion of a transistor may be prevented. Moreover, charge carrier entrapment in the active areas may be reduced since barrier atoms have terminated many of the dangling bonds. Since Sixe2x80x94N bonds are stronger and less strained than Sixe2x80x94O bonds, nitrogen barrier atoms are better suited for inhibiting the immobility of charge carriers near the edges of a transistor.